®
CMOS ST-BUS™ FAMILY
MT9079
Advanced Controller for E1
Features
•
Meets applicable requirements of CCITT
G.704, G.706, G.732, G.775, G.796, I.431 and
ETSI ETS 300 011
HDB3, RZ, NRZ (fibre interface) and bipolar
NRZ line codes
Data link access and national bit buffers (five
bytes each)
Enhanced alarms, performance monitoring and
error insertion
Maskable interrupts for alarms, receive CAS bit
changes, exception conditions and counter
overflows
Automatic interworking between CRC-4 and
non-CRC-4 multiframing
Dual transmit and receive 16 byte circular
channel buffers
Two frame receive elastic buffer with controlled
slip direction indication and 26 channel
hysteresis (208 UI wander tolerance)
CRC-4 updating algorithm for intermediate path
points of a message-based data link application
ISSUE 2
May 1995
•
•
•
•
Ordering Information
MT9079AC
40 Pin Ceramic DIP
MT9079AE
40 Pin Plastic DIP
MT9079AL
44 Pin QFP
MT9079AP
44 Pin PLCC
-40° to 85°C
Description
The MT9079 is a feature rich E1 (PCM 30, 2.048
Mbps) link framer and controller that meets the latest
CCITT and ETSI requirements.
The MT9079 will interface to a 2.048 Mbps
backplane and can be controlled directly by a
parallel processor, serial controller or through the
ST-BUS.
Extensive alarm transmission and reporting, as well
as exhaustive performance monitoring and error
diagnostic features make this device ideal for a wide
variety of applications.
•
•
•
•
Applications
•
•
•
•
•
Primary rate ISDN network nodes
Digital Access Cross-connect (DACs)
CO and PABX switching equipment interfaces
E1 add/drop multiplexers and channel banks
Test equipment and satellite interfaces
TxMF
RxMF
DSTi
DSTo
Transmit & Receive
Data
Interface
Frame MUX/DEMUX
2 Frame Rx
Elastic
Buffer With
Slip Control
PCM 30
(E1)
Link
Interface
TAIS
TxA
TxB
RxA
RxB
TxDL
RxDL
DLCLK
Data
Link
Buffer
National
Bit
Buffer
Dual 16
Byte Rx
Buffer
Dual 16
Byte Tx
Buffer
Performance
Monitoring &
Alarm
Control
Phase
Detector
÷
256
Circuit
Timing
E2i
E8Ko
Control
Port
Interface
(fig. 3)
Control
Interface
ABCD
Signal
Buffer
Test
Code
Gen.
V
DD
V
SS
IC
C4i/C2i
F0i
ST-BUS Timing
Circuit
Timing
to all registers
and counters
RESET
Figure 1 - Functional Block Diagram
4-237
MT9079
NC
DLCLK
TxDL
RxDL
DSTo
RESET
IC
TxA
TxB
TAIS
CSTo1
IRQ
D0\SIO\CSTo0
D1
D2
D3
D4
D5
D6
D7
VDD
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
CSTi2
VSS
S/P
TxMF
RxMF
DSTi
E8Ko
F0i
RxA
RxB
39
38
37
36
35
34
33
32
31
30
29
NC
CSTi2
VSS
S/P
TxMF
RxMF
DSTi
E8Ko
F0i
RxA
RxB
A4\ST/SC
AC3
AC2
AC1
AC0
R/W\RxD\CSTi0
CS
DS\SCLK\CSTi1
C4i/C2i
E2i
NC
44 PIN QFP
NC
DLCLK
TxDL
RxDL
DSTo
RESET
IC
TxA
TxB
TAIS
CSTo1
12
13
14
15
16
17
18
19
20
21
22
RESET
DSTo
RxDL
TxDL
DLCLK
IRQ
D0\SIO\CSTo0
D1
D2
D3
D4
D5
D6
D7
VDD
AC4\ST/SC
AC3
AC2
AC1
AC0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IC
TxA
TxB
TAIS
CSTo1
CSTi2
VSS
S/P
TxMF
RxMF
DSTi
E8Ko
F0i
RxA
RxB
E2i
C4i/C2i
DS\SCLK\CSTi1
CS
R/W\RxD\CSTi0
40 PIN CERDIP/PLASTIC DIP
IRQ
D0\SIO\CSTo0
D1
D2
D3
D4
D5
D6
D7
VDD
NC
Figure 2 - Pin Connection
4-238
A4\ST/SC
AC3
AC2
AC1
AC0
R/W\RxD\CSTi0
CS
DS\SCLK\CSTi1
C4i/C2i
E2i
NC
44 PIN PLCC
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
MT9079
Pin Description
Pin #
DIP
PLCC
QFP
Name
39
Description (see notes 1, 2 and 3)
1
1
RESET
RESET (Input):
Low - maintains the device in a reset condition. High - normal
operation. The MT9079 should be reset after power-up. The time constant for a
power-up reset circuit (see Figure 11) must be a minimum of five times the rise time of
the power supply. In normal operation, the RESET pin must be held low for a minimum
of 100 nsec. to reset the device.
DSTo
RxDL
Data ST-BUS (Output):
A 2.048 Mbit/s serial output stream which contains the 30
PCM or data channels received from the PCM 30 line. See Figure 4b.
Receive Data Link (Output):
A 4 kbit/s serial stream which is demultiplexed from a
selected national bit (non-frame alignment signal) of the PCM 30 receive signal.
Received DL data is clocked out on the rising edge of DLCLK, see Figure 20.
Transmit Data Link (Input):
A 4 kbit/s serial stream which is multiplexed into a
selected national bit (non-frame alignment signal) of the PCM 30 transmit signal.
Transmit DL data is clocked in on the rising edge of internal clock IDCLK, see Figure
21.
2
3
2
3
40
41
4
4
42
TxDL
5
5
43
DLCLK
Data Link Clock (Output):
A 4 kHz clock signal used to clock out DL data (RxDL) on
its rising edge. It can also be used to clock DL data in and out of external serial
controllers (i.e., MT8952). See TxDL and RxDL pin descriptions.
NC
IRQ
No Connection.
Interrupt Request (Output):
Low - interrupt request. High - no interrupt request.
IRQ is an open drain output that should be connected to V
DD
through a pull-up resistor.
An active CS signal is not required for this pin to function.
Data 0 (Three-state I/O):
The least significant bit of the bidirectional data bus of the
parallel processor interface.
Serial Input/Output (Three state I/O):
This pin function is used in serial controller
mode and can be configured as control data input/output for Intel operation (connect
to controller pin RxD). Input data is sampled LSB first on the rising edge of SCLK; data
is output LSB first on the falling edge of SCLK. It can also be configured as the control
data output for Motorola and National Microwire operation (data output MSB first on
the falling edge of SCLK). See CS pin description.
-
6
6
7
44
1
7
8
2
D0
[P]
SIO
[S]
CSTo0
Control ST-BUS Zero (Output):
A 2.048 Mbit/s serial status stream which provides
[ST] device status, performance monitoring, alarm status and phase status data.
8-14 9-15 3-9
15
-
16
16
17
18
10
11
12
D1-D7
Data 1 to Data 7 (Three-state I/O):
These signals, combined with D0, form the
[P]
bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
V
DD
NC
AC4
[P]
Positive Power Supply (Input):
+5V
±
10%.
No Connection.
Address/Control 4 (Input):
The most significant address and control input for the
non-multiplexed parallel processor interface.
ST/SC
ST-BUS/Serial Controller (Input):
High - selects ST-BUS mode of operation.
[ST S] Low - selects serial controller mode of operation.
17-
20
19-
22
13- AC3-AC
Address/Control 3 to 0 (Inputs):
Address and control inputs for
16
0
non-multiplexed parallel processor interface. AC0 is the least significant input.
[P]
the
4-239
MT9079
Pin Description (Continued)
Pin #
DIP
PLCC
QFP
Name
17
R/W
[P]
RxD
[S]
Description (see notes 1, 2 and 3)
Read/Write (Input):
High - the parallel processor is reading data from the MT9079.
Low - the parallel processor is writing data to the MT9079.
Receive Data (Input):
This pin function is used in Motorola and National Microwire
serial controller mode. Data is sampled on the rising edge of SCLK, MSB first. See
CS pin description.
Control ST-BUS Zero (Input):
A 2.048 Mbit/s serial control stream which contains
the device control, mode selection, and performance monitoring control.
Chip Select (Input):
Low - selects the MT9079 parallel processor or serial controller
interface. High - the parallel processor or serial controller interface is idle and all
bus I/O pins will be in a high impedance state. When controller mode is selected,
the SCLK input is sampled when CS is brought low. If SCLK is high the device in is
Intel mode; if SCLK is low it will be in Motorola/National Microwire mode. This pin
has no function (NC) in ST-BUS mode.
Data Strobe (Input):
This input is the active low data strobe of the parallel
processor interface.
Serial Clock (Input):
This is used in serial controller mode to clock serial data in
and out of the MT9079 on RxD and SIO. If SCLK is high when CS goes low, the
device will be in Intel mode; if SCLK is low when CS goes low, it will be in
Motorola/National Microwire mode.
Control ST-BUS One (Input):
A 2.048 Mbit/s serial control stream which contains
the per timeslot control programming.
21
23
CSTi0
[ST]
22
24
18
CS
[SP]
23
25
19
DS
[P]
SCLK
[S]
CSTi1
[ST]
24
26
20
C4i/C2i
4.096 MHz and 2.048 MHz System Clock (Input):
This is master clock for the serial
PCM data and ST-BUS sections of the MT9079. The MT9079 automatically detects
whether a 4.096 or 2.048 MHz clock is being used. See Figure 22 for timing
information.
E2i
2.048 MHz Extracted Clock (Input):
This clock is extracted from the received
signal. Its rising edge is used internally to clock in data received on RxA and RxB.
See Figure 29.
No Connection.
Receive B (Input):
Received split phase unipolar signal decoded from a bipolar line
receiver. Receives RZ and NRZ bipolar signals. See Figures 29 and 31.
Receive A (Input):
Received split phase unipolar signal decoded from a bipolar line
receiver. Receives RZ and NRZ bipolar signals. See Figurs 29 and 31.
Frame Pulse (Input):
This is the ST-BUS frame synchronization signal which
delimits the 32 channel frame of all ST-BUS streams, as well as DSTi and DSTo in
all modes.
Extracted 8 kHz Clock (Output):
An 8 kHz signal generated by dividing the
extracted 2.048 MHz clock (E2i) by 256 and aligning it with the received PCM 30
frame. The 8 kHz signal can be used to synchronize the system clock with the
extracted 2.048 MHz clock. E8Ko is high when 8KSEL=0. See Figure 27.
Data ST-BUS (Input).
A 2.048 Mbit/s serial stream which contains the 30 PCM or
data channels to be transmitted on the PCM 30 line. See Figure 4a.
25
27
21
-
26
27
28
28
29
30
31
22
23
24
25
NC
RxB
RxA
F0i
29
32
26
E8Ko
30
33
27
DSTi
4-240
MT9079
Pin Description (Continued)
Pin #
DIP
PLCC
QFP
Name
28
RxMF
Description (see notes 1, 2 and 3)
Receive Multiframe Boundary (Output):
An output pulse delimiting the received
multiframe boundary. The next frame output on the data stream (DSTo) is basic frame
zero on the PCM 30 link. This receive multiframe signal can be related to either the
receive CRC multiframe (MFSEL=1) or the receive signalling multiframe (MFSEL=0).
See Figures 25 and 26.
Transmit Multiframe Boundary (Input):
This input is used to set the channel
associated and CRC transmit multiframe boundary. The device will generate its own
multiframe if this pin is held high. This input is pulled high in most applications. See
Figures 24 to 26.
Serial/Parallel (Input):
High - serial controller port or ST-BUS operation.
Low - parallel processor port operation.
Negative Power Supply (Input):
Ground.
Control ST-BUS Input Two (Input):
A 2.048 Mbit/s ST-BUS control stream which
contains the 30 (ABCDXXXX) transmit signalling nibbles when RPSIG=0. When
RPSIG=1 this pin has no function. Only the most significant nibbles of each ST-BUS
timeslot are valid. See Figure 4c.
No Connection.
31
34
32
35
29
TxMF
33
34
35
36
37
38
30
31
32
S/P
V
SS
CSTi2
-
36
37
38
39
40
41
42
33
34
35
36
NC
CSTo1
Control ST-BUS Output One (Output):
A 2.048 Mbit/s serial status stream which
provides the 30 (ABCDXXXX) receive signalling nibbles.
TAIS
TxB
Transmit Alarm Indication Signal (Input):
High - TxA and TxB will transmit data
normally. Low - TxA and TxB transmits an AIS (all ones signal).
Transmit B (Output):
A split phase unipolar signal suitable for use with TxA, an
external line driver and a transformer to construct a bipolar PCM 30 line signal. This
output can also transmit RZ and NRZ bipolar signals. See Figures 28 and 30.
Transmit A (Output):A
split phase unipolar signal suitable for use with TxB, an
external line driver and a transformer to construct a bipolar PCM 30 line signal. This
output can also transmit RZ and NRZ bipolar signals. See Figures 28 and 30.
Internal Connection (Input):
Connect to ground for normal operation.
39
43
37
TxA
40
44
38
IC
Notes:
1. All inputs are CMOS with TTL compatible logic levels.
2. All outputs are CMOS and are compatible with both TTL and CMOS logic levels.
3. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for input and output
voltage thresholds.
4-241
